1. Field of the Invention
The present invention relates to a digital-to-analog converter of a data driver for a display device and a converting method thereof, and more particularly, to a digital-to-analog converter of a data driver and a converting method thereof, in which information corresponding to a lower bit is converted into an analog signal through control of current transmission paths and control of a transconductance ratio.
2. Description of the Related Art
A liquid crystal display (LCD) is one of flat panel displays in which image data is displayed by passing light through liquid crystals using a characteristic that an aligned state of liquid crystal molecules is changed depending upon an applied voltage.
FIG. 1 is a block diagram illustrating the configuration of a conventional liquid crystal display device.
Referring to FIG. 1, a conventional liquid crystal display device includes a timing controller 10, a data driver 20, a gate driver 40, and a panel 30.
The timing controller 10 is configured to transfer timing signals (such as a clock signal, a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, etc.) for controlling the gate driver 40 and the data driver 20 and RGB data signals to the data driver 20 and the gate driver 40.
The data driver 20 is configured to receive the RGB data outputted from the timing controller 10 and data driver control signals and output data to the panel 30 by the unit of line in response to the horizontal synchronization signal.
The gate driver 40 is configured to receive gate driver control signals which are outputted from the timing controller 10 and drive a plurality of gate lines. The gate driver 40 controls the gate lines in order to sequentially output the data outputted from the data driver 20 to the panel 30.
FIG. 2 is a view illustrating an exemplary data driver of the liquid crystal display device shown in FIG. 1.
Referring to FIG. 2, a data driver 21 includes a control section 300 for transferring timing control signals, a shift register section 310, a data register section 320, a latch section 330, a level shifter (not shown), a digital-to-analog converter 340, and an output buffer 350.
The control section 300 is configured to receive a clock signal CLK and timing control signals LOAD and POL from an outside, supply the clock signal CLK to the shift register section 310, and transfer the timing control signals LOAD and POL to the latch section 330 and the output buffer 350.
The data register section 320 is configured to output RGB data signals to the latch section 330 based on the inputted clock signal. Meanwhile, the shift register 310 is configured to sequentially perform a shifting operation for the inputted clock signal and output the shifted clock signal to the latch section 330.
The latch section 330 is configured to latch and store the RGB data signals based on the shifted clock signal.
The level shifter (not shown) is configured to raise the digital voltage stored in the latch section 330 to an analog voltage range and output the resultant signal to the digital-to-analog converter 340. The digital-to-analog converter 340 is configured to receive digital data corresponding to each line of the stored image from the level shifter, convert the digital data into analog data using a gamma reference voltage which is independent for respective channels, and output the analog data to the output buffer 350.
The output buffer 350 is configured to output the analog data converted by the digital-to-analog converter 340 to the panel 30 in response to data driver control signals.
FIG. 3 is a view illustrating a digital-to-analog converter used in the data driver shown in FIG. 2.
Referring to FIG. 3, the conventional digital-to-analog converter 340 includes resistor strings and switches. The resistor strings supply gray-scale voltages, and the switches select the gray-scale voltages depending upon the data inputted thereto and output the gray-scale voltages to the output buffer 350. However, in the conventional digital-to-analog converter which uses the resistor strings, if the number of digital bits of data is increased, problems are caused in that the number of switches increases by geometric progression and the area of an entire circuit increases.
That is to say, since an area increases 2N times when data increases by N bits, in order to apply a digital-to-analog converter to an application field of a data driver with a high gray scale, it is necessary to reduce the area of the digital-to-analog converter. Accordingly, in order to reduce the area of the digital-to-analog converter, an interpolation method has been suggested in the art.
FIG. 4 is a configuration diagram illustrating a conventional interpolation type digital-to-analog converter.
Referring to FIG. 4, a conventional interpolation type digital-to-analog converter includes an analog gray-scale voltage generation stage 410, a first decoder 420, a second decoder 430, and an interpolated voltage generation stage 440.
The analog gray-scale voltage generation stage 410 is constituted by a string of a plurality of resistors which are connected in series between VgammaH and VgammaL, and is configured to generate analog gray-scale voltages of 2K (=J) levels through division by the respective resistors.
The first decoder 420 is configured to generate a first level voltage Vh and a second level voltage Vl among the analog gray-scale voltages of 2K (=J) levels in response to image data of upper K bits among entire image data of N bits (for example, 8 or 10 bits).
The second decoder 430 is configured to divide the first level voltage Vh and the second level voltage Vl in response to image data of remaining lower L bits among the entire image data of N bits and output M number of divided outputs.
The interpolated voltage generation stage 440 is configured to generate interpolated voltages corresponding to the M number of divided outputs and drive the data lines of a panel.
In such an interpolation method, in the case of the upper K bits among the entire N bits of digital image data, representative gray-scale voltages are selected by a digital-to-analog converter structure using the existing resistor string, and in the case of the remaining lower L bits, divided output voltages are generated by dividing the selected gray-scale voltages through interpolation.
However, in such a conventional interpolation type digital-to-analog converter, as the number of the lower L bits to be interpolated increases, the linearity of an output voltage deteriorates, and therefore, it is difficult to decrease the number of upper K bits for outputting voltages through the resistor string to or below 8 bits. As a consequence, a problem is caused in that it is necessary to provide additional transistors on an input side.